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ht82j97e/ht82j97a usb joystick encoder 8-bit mcu block diagram rev. 1.60 1 december 23, 2008 general description the usb mcu otp body is suitable for usb mouse and usb joystick devices. it consists of a holtek high performance 8-bit mcu core for control unit, built-in usb sie, 2k 14 eprom and 96 bytes data ram. features flexible total solution for applications that combine ps/2 and low-speed usb interface, such as mice, joysticks, and many others usb specification compliance conforms to usb specification v1.1 conforms to usb hid specification v1.1 supports 1 low-speed usb control endpoint and 1 interrupt endpoint each endpoint has 8 8 bytes fifo integrated usb transceiver 3.3v regulator output external 6mhz or 12mhz ceramic resonator or crystal 8-bit risc microcontroller, with 2k 14 eprom (000h~7ffh) 96 bytes ram (20h~7fh) 6mhz/12mhz internal cpu clock 4-level stacks two 8-bit indirect addressing registers one 16-bit programmable timer counter with over - flow interrupt (shared with pa7, vector 0ch) one usb interrupt input (vector 04h) halt function and wake-up feature reduce power consumption pa0~pa7 support wake-up function internal power-on reset (por) watchdog timer (wdt) 20 i/o ports (including 2-pwm output, pc2, pc3) 2 pwm output (pc2, pc3) can produce pwm frequency range from 23hz to 23khz built-in 8-bit analog-to-digital converter, (6-channel for internal mode (pb0~pb5), 6-channel for external mode with vhl (pb7) and vrl (pb6)) 20/28-pin sop package

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pin assignment pin description pin name i/o rom code option description pa0~pa7 i/o pull-low pull-high wake-up cmos/nmos/pmos bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by rom code option. the input or output mode is con - trolled by pac (pa control register). pull-high resistor options: pa0~pa7 pull-low resistor options: pa0~pa3 cmos/nmos/pmos options: pa0~pa7 wake-up options: pa0~pa7 pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb5/an5 pb6/vrl i/o pull-high analog input bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options). the pb can be used as analog input of the analog to digital converter (determined by options). pull-low resistor for options: pb2, pb3 pb4/an4 pb7/vrh i/o pull-high analog input wake-up bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options). the pb can be used as analog input of the analog to digital converter (determined by options). wake-up options: pb4, pb7 vss negative power supply, ground pc0~pc3 i/o pull-high bidirectional i/o lines. software instructions determine the cmos out - put or schmitt trigger input with pull-high resistor (determined by pull-high options). pc2 can be used as pwm1 output pc3 can be used as pwm2 output res i schmitt trigger reset input. active low. vdd positive power supply v33o o 3.3v regulator output usbd+/clk i/o usbd+ or ps2 clk i/o line usb or ps2 function is controlled by software control register usbd-/data i/o usbd- or ps2 data i/o line usb or ps2 function is controlled by software control register osci osco i o osci, osco are connected to a 6mhz or 12mhz crystal/resonator (determined by software instructions) for the internal system clock. ht82j97e/ht82j97a rev. 1.60 2 december 23, 2008 8 9 1 0 / * 7 7 * / 0 1 9 8
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absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature...............................0 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 4 5.5 v i dd operating current (6mhz crystal) 5v no load, f sys =6mhz 79ma i stb standby current 5v no load, system halt 300 500 a v il1 input low voltage for i/o ports 5v 0 0.8 v v ih1 input high voltage for i/o ports 5v 2 5v v il2 input low voltage (res )5v 0 0.4v dd v v ih2 input high voltage (res )5v 0.9v dd v dd v i ol output sink current for other ports pa0~pa7, pb0~pb7 and pc0~pc3 5v v ol =0.4v 24 ma i oh output port source current 5v v ol =3.4v 2.5 4 ma r pd pull-down resistance for pa0~pa3, pb2 and pb3 5v 10 30 50 k r ph1 pull-high resistance for clk and data 2 4.7 6 k r ph2 pull-high resistance for pa0~pa7, pb0~pb7 and pc0~pc3 30 50 70 k v lvr low voltage reset 5v 2.4 2.7 3 v a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 6 12 mhz f rcsys rc clock with 8-bit prescaler register 5v 032 khz t wdt watchdog time-out period (system clock) without wdt prescaler 1024 t rcsys t rf usbd+, usbd- rising & falling time 75 300 ns t sst system start-up timer period wake-up from halt 1024 t sys t osc crystal setup 510ms f pwm pwm cycle frequency 6mhz or 12mhz 23 2300 hz note: power-on period=t wdt +t sst +t osc wdt time-out in normal mode=1/f rcsys 256 wdts+t wdt wdt time-out in halt mode=1/f rcsys 256 wdts+t sst +t osc ht82j97e/ht82j97a rev. 1.60 3 december 23, 2008
ht82j97e/ht82j97a rev. 1.60 4 december 23, 2008 functional description execution flow the system clock for the microcontroller is derived from either 6mhz or 12mhz crystal oscillator, which used a frequency that is determined by the sclksel bit of the scc register. the default system frequency is 12mhz. the system clock is internally divided into four non- overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to be effectively executed in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading to the pcl register, performing a sub - routine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from inter - rupts, the pc manipulates the program transfer by load - ing the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. 7 * 7 * 7 * : $ ( ( ; < = ( ( ; 6 < : $ ( ( ; 5 < = ( ( ; < : $ ( ( ; 5 < = ( ( ; 5 < 5 5 ! ( , > ( ; ( , < execution flow mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 usb interrupt 00000000100 timer/event counter overflow 00000001100 skip program counter+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits
ht82j97e/ht82j97a rev. 1.60 5 december 23, 2008 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 2048 14 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after a chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 00ch this location is reserved for the timer/event counter interrupt service program. if a timer interrupt results from a timer/event counter overflow, and the inter - rupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. there are three method to read the rom data by two table read instructions: tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows: the instructions tabrdc [m] (the current page, one page=256words), where the table locations is defined by tblp (07h) in the current page. and the rom code option tbhp is disabled (default). the instructions tabrdc [m] , where the table lo - cations is defined by registers tblp (07h) and tbhp (01fh). and the rom code option tbhp is enabled. the instructions tabrdl [m] , where the table lo - cations is defined by registers tblp (07h) in the last page (0700h~07ffh). only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh , and the re - maining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the ta - ble pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before ac - cessing the table, the location must be placed in the tblp and tbhp (if the otp option tbhp is disabled, the value in tbhp has no effect). the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main rou- tine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the require - ments. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp value. otherwise, the rom code option tbhp is dis - abled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. * ( - ! 1 : : 2 : : 2
# > 6 ( ? , ( ; / 0 ( + " ! < # > 6 ( ? , ( ; / 0 ( + " ! < @ ( ( ! ( % ( ( ( 1 2 2 3 ( , a ( - ( ( ? * 2 2 ) 3 ( ( ? ( program memory instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits p10~p8: current program counter bits when tbhp is disabled @7~@0: tblp bits tbhp register bit2~bit0 when tbhp is enabled
ht82j97e/ht82j97a rev. 1.60 6 december 23, 2008 stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 4 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 return ad - dresses are stored). data memory ram for bank 0 the data memory is designed with 96 8 bits. the data memory is divided into two functional groups: special function registers and general purpose data memory (96 8). most are read/write, but some are read only. the special function registers include the indirect ad- dressing registers (r0;00h, r1;02h), bank register (bp, 04h), pwm1 duty register (0dh), pwm2 duty regis- ter(0eh), timer/event counter higher order byte regis - ter (tmrh;0fh), timer/event counter lower order byte register (tmrl;10h), timer/event counter control reg - ister (tmrc;11h), program counter lower-order byte register (pcl;06h), memory pointer registers (mp0;01h, mp1;03h), accumulator (acc;05h), table pointers (tblp;07h, tbhp;1fh), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h), pwm base period register (18h), i/o control registers (pac;13h, pbc;15h, pcc;17h). usb/ps2 status and control reg - ister (usc;1ah), usb endpoint interrupt status register (usr;1bh), system clock control register (scc;1ch). a/d converter status and control register (adsc;1dh) and a/d converter result register (adr;1eh). the re - maining space before the 20h is reserved for future ex - panded usage and reading these locations will get 00h . the general purpose data memory, addressed from 20h to 7fh, is used for data and control informa - tion under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). 2 2 2 7 2 * 2 / 2 0 2 1 2 9 2 8 2 2 - 2 2 2 2 : 2 2 2 2 7 2 * 2 / 2 0 2 1 2 9 2 & , ( ! (

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ht82j97e/ht82j97a rev. 1.60 7 december 23, 2008 data memory ram for bank 1 the special function registers used in the usb interface are located in ram bank1. in order to access bank1 register, only the indirect addressing pointer mp1 can be used and the bank register bp should be set to 1. the ram bank 1 mapping is as shown. address 00~1fh in ram bank0 and bank1 are located in the same registers indirect addressing register locations 00h and 02h are indirect addressing regis - ters that are not physically implemented. any read/write operation on [00h] ([02h]) will access the data memory pointed to by mp0 (mp1). reading location 00h (02h) indirectly will return the result 00h. writing indirectly re - sults in no operation. the indirect addressing pointer (mp0) always points to bank0 ram addresses no matter the value of bank register (bp). the indirect addressing pointer (mp1) can access bank0 or bank1 ram data according to the value of bp which is set to 0 or 1 respectively. the memory pointer registers (mp0 and mp1) are 7-bit registers. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults from those intended. 2 2 2 7 2 * 2 / 2 0 2 1 2 9 2 8 2 2 - 2 2 2 2 : 2 2 2 2 7 2 * 2 / 2 0 2 1 2 9 2 2 - 2 2 2 2 : 2 2 " ( " " ! ! ( ! (
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ht82j97e/ht82j97a rev. 1.60 8 december 23, 2008 the to flag can be affected only by a system power-up, a wdt time-out or executing the clr wdt or halt instruction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, upon entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre- vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at a specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. bit no. label function 0 emi controls the master (global) interrupt (1=enable; 0=disable) 1 eui controls the usb interrupt (1=enable; 0= disable) 2 unused bit, read as 0 3 eti controls the timer/event counter interrupt (1=enable; 0=disable) 4 usbf usb interrupt request flag (1=active; 0=inactive) 5 unused bit, read as 0 6 tf internal timer/event counter request flag (1:active; 0:inactive) 7 unused bit, read as 0 intc (0bh) register bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6 unused bit, read as 0 7 unused bit, read as 0 status (0ah) register
ht82j97e/ht82j97a rev. 1.60 9 december 23, 2008 the usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of the intc) will be set. access of the corresponding usb fifo from pc the usb suspend signal from pc the usb resume signal from pc usb reset signal when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca - tion 04h will occur. the interrupt request flag (usbf) and emi bits will be cleared to disable other interrupts. when the pc host access the fifo of the ht82j97e/ ht82j97a, the corresponding request bit of the usr is set, and a usb interrupt is triggered. so user can easily decide which fifo is accessed. when the interrupt has been served, the corresponding bit should be cleared by firmware. when the ht82j97e/ht82j97a receives a usb suspend signal from the host program counter, the suspend line (bit0 of the usc) of the ht82j97e/ ht82j97a is set and a usb interrupt is also triggered. when the ht82j97e/ht82j97a receives a resume signal from the host program counter, the resume line (bit3 of the usc) of the ht82j97e/ht82j97a is set and a usb interrupt is triggered. whenever a usb reset signal is detected, the usb in- terrupt is triggered and urst_flag bit of the usc regis- ter is set. when the interrupt has been served, the bit should be cleared by firmware. the internal timer/even counter interrupt is initialized by setting the timer/event counter interrupt request flag (;bit 6 of the intc), caused by a timer overflow. when the in- terrupt is enabled, the stack is not full and the tf is set, a subroutine call to location 0ch will occur. the related in- terrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. no. interrupt source priority vector a usb interrupt 1 04h b timer/event counter overflow 2 0ch the timer/event counter interrupt request flag (tf), usb interrupt request flag (usbf), enable timer/event coun - ter interrupt bit (eti), enable usb interrupt bit (eui) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eui and eti are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the inter - rupt request flags (tf, usbf) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there is an oscillator circuit in the microcontroller. this oscillator is designed for system clocks. the halt mode stops the system oscillator and ignores an exter- nal signal to conserve power. a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. in stead of a crystal, a resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. the ht82j97e/ht82j97a can operate in 6mhz or 12mhz system clocks. in order to make sure that the usb sie functions properly, user should correctly con - figure the sclksel bit of the scc register. the default system clock is 12mhz. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works within a period of approximately 31 s. the wdt oscillator can be disabled by rom code option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), or instruction clock (sys - ! , ( ! , , system oscillator
ht82j97e/ht82j97a rev. 1.60 10 december 23, 2008 tem clock divided by 4), determine by rom code option. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be dis - abled by rom code option. if the watchdog timer is dis - abled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 31 s/5v normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5v. this time-out period may vary with tempera - tures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bits 2, 1, 0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 1s/5v. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are re- served for user defined flags, which can only be set to 10000 (wdts.7~wdts.3). if the device operates in a noisy environment, using the on-chip 32khz rc oscillator (wdt osc) is strongly rec - ommended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize a chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the program counter and sp are reset to zero. to clear the contents of the wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instruction and a halt in - struction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 .of these two types of instruction, only one can be active de - pending on the rom code option clr wdt times se - lection option .ifthe clr wdt is selected (i.e. clrwdt times is equal to one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt and clr wdt are chosen (i.e. clrwdt times is equal to two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following: the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se- lected). the contents of the on-chip ram and registers remain unchanged. the wdt and wdt prescaler will be cleared and re- counted again (if the wdt clock is from the wdt os- cillator). all of the i/o ports remain in their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the cause for chip reset can be determined. the pdf flag is cleared by a system power-up or exe - cuting the clr wdt instruction and is set when exe - cuting the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others remain in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by mask option. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the inter - rupt is enabled but the stack is full, the program will re - ! ( , > ) * 9 6 ? ( + ( ! , 1 6 ? ( 9 6 6 (
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ht82j97e/ht82j97a rev. 1.60 11 december 23, 2008 sume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt re - sponse takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are four ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation usb reset the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav- ing the other circuits in their original state. some regis- ters remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up 0 0 res reset during normal operation 0 0 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulses when the sys - tem resets (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack reset circuit + ( ! + 2 # , " ! ! ( ! 6 ? ( , reset configuration ( 6 $ ( ( ! reset timing chart
ht82j97e/ht82j97a rev. 1.60 12 december 23, 2008 the registers status are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb-reset (normal) usb-reset (halt) tmrh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrl xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrc 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- program counter 000h 000h 000h 000h 000h 000h 000h mp0 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu mp1 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc -000 0000 -000 0000 --00 uuuu -000 0000 -uuu uuuu -000 0000 -000 0000 wdts 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pipe 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 sies 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 usc 11xx 0000 uuxx uuuu 11xx 0000 11xx 0000 uuxx uuuu 1100 0u00 1100 0u00 usr 0100 0000 uuuu uuuu 0100 0000 0100 0000 uuuu uuuu u1uu 0000 u1uu 0000 scc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uu00 u000 uu00 u000 adsc 1000 0000 uuuu uuuu 1000 0000 1000 0000 uuuu uuuu 1000 0000 1000 0000 adr xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx note: * stands for warm reset u stands for unchanged x stands for unknown
ht82j97e/ht82j97a rev. 1.60 13 december 23, 2008 bit no. label function 0~2 unused bit, read as 0 3te defines the tmr active edge of the timer/event counter (0=active on low to high; 1=active on high to low) 4 ton enable/disable the timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 tm0 tm1 defines the operating mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc (11h) register timer/event counter a timer/event counter (tmr) is implemented in the microcontroller. the timer/event counter contains a 16-bit programma - ble count-up counter and the clock may come from an external source or from the system clock divided by 4. using the internal clock source, there is only 1 reference time-base for the timer/event counter. the internal clock source is coming from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths. there are 3 registers related to the timer/event counter; tmrh (0fh), tmrl (10h), tmrc (11h). writing tmrl will only put the written data to an internal lower-order byte buffer (8 bits) and writing tmrh will transfer the specified data and the contents of the lower-order byte buffer to tmrh and tmrl preload registers, respec - tively. the timer/event counter preload register is changed by each writing tmrh operations. reading tmrh will latch the contents of tmrh and tmrl coun - ters to the destination and the lower-order byte buffer, respectively. reading the tmrl will read the contents of the lower-order byte buffer. the tmrc is the timer/event counter control register, which defines the operating mode, counting enable or disable and active edge. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means that the clock source comes from an exter - nal (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the f sys /4 (timer). the pulse width measurement mode can be used to count the high or low level duration of the exter - nal signal (tmr). the counting is based on the f sys /4. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (tf; bit 6 of the intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a tran - sient from low to high (or high to low if the te bit is 0 )it will start counting until the tmr returns to the original level and resets the ton. the measured result will re - main in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transient pulse. note that, in this operat - ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on

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# < # c ( - - % % timer/event counter
ht82j97e/ht82j97a rev. 1.60 14 december 23, 2008 bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared au - tomatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the opera - tion mode is, writing a 0 to et can disable the corre - sponding interrupt services. in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs (a timer/event counter reloading will occur at the same time). when the timer/event counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may result in a counting error, this must be taken into consideration by the programmer. input/output ports there are 20 bidirectional input/output lines in the microcontroller, labeled from pa to pc, which are mapped to the data memory of [12h], [14h] and [16h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h or 16h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc) to control the input/output configuration. with this control register, cmos/nmos/pmos output or schmitt trigger input with or without pull-high/low resistor struc- tures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must write a 1 . the input source also depends on the control register. if the control regis - ter bit is 1 , the input will read the pad state. if the con - trol register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos/nmos/pmos configurations can be selected (nmos and pmos are available for pa only). these control registers are mapped to locations 13h, 15h and 17h. after a chip reset, these input/output lines remain at high levels or in a floating state (depending on the pull-high/low options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h or 16h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. there are pull-high/low (pa only) options available for i/o lines. once the pull-high/low option of an i/o line is selected, the i/o line have pull-high/low resistor. other- wise, the pull-high/low resistor is absent. it should be noted that a non-pull-high/low i/o line operating in input mode will cause a floating state. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. . 0 d ( 1 )
- ) . - / ) / - 0 ) # d ( - 1 ) 2 . 7
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. / d # d 2 ( % input/output ports note: the outputs of pc2 and pc3 will be pwm outputs when pwm outputs are enabled.
ht82j97e/ht82j97a rev. 1.60 15 december 23, 2008 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device drops to within the range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage (0.9v~v lvr ) must exist for more than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not per - form a reset function. the lvr uses the or function with the external res signal to perform a chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera - tion at 6mhz or 12mhz system clock. / 4 / 4 8 # / 4 / 4 1 4 * / 4 / # 4 8 ! ( , ! f f , ( ! # ( ( , low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: a low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
ht82j97e/ht82j97a rev. 1.60 16 december 23, 2008 usb with mcu interface there are eight registers, including pipe_ctrl, address+remote_wakeup, stall, pipe, sies, misc, fifo 0 and fifo 1 in this buffer function. register name pipe_ctrl addr.+remote stall pipe sies misc fifo 0 fifo 1 mem. addr. 41h 42h 43h 44h 45h 46h 48h 49h reserved addr. bank 1, address 40h, 4ah, 4fh register memory mapping address+remote_wakeup register represents current address and remote wake-up function. the initial value is 00000000 from msb to lsb. register address r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01000010b r/w address value default value=00000000 remote wake-up function 0: not this function 1: the function exists address+remote_wakeup register the pipe_ctrl, stall and pipe are bitmap ones. the pipe_ctrl register is used for configuring in (bit=1) or out (bit=0) pipe. the default is defined as in pipe. the pipe register represents whether the corresponding endpoint is ac - cessed by host or not. after a usb interrupt signal is being sent out, the mcu can check which endpoint had been ac - cessed. this register is set only after the host accessed the corresponding endpoint. the stall register shows whether the corresponding endpoint works or not. as soon as the endpoint works improperly, the corresponding bit must be set. the bitmaps are listed as follows: register name r/w register address bit7~bit2 reserved bit 1 bit 0 default value pipe_ctrl r/w 01000001b pipe 1 pipe 0 00000011 stall r/w 01000011b pipe 1 pipe 0 00000000 pipe r 01000100b pipe 1 pipe 0 00000000 stall (43h) and pipe (44h) registers
ht82j97e/ht82j97a rev. 1.60 17 december 23, 2008 the sies register is used to indicate the present signal state which the usb sie received and also determines whether the usb sie has to change the device address automatically. bit no. function read/write register address 7 mni r/w 01000101b 6~2 1 f0_err r/w 0 adr_set r/w sies (45h) registers table bit no. function name description 0 adr_set this bit is used to configure the usb sie to automatically change the device address with the value of the address+remote_wakeup register (42h). when this bit is set to 1 by f/w, the usb sie will update the device address with the value of the address+remote_wakeup register (42h) after the pc host has successfully read the data from the device by the in operation. the usb sie will clear the bit after updating the device address. otherwise, when this bit is cleared to 0, the usb sie will update the device address imme - diately after an address is written to the address+remote_wakeup register (42h). 1 f0_err this bit is used to indicate when there are some errors that occurred when the fifo0 is ac - cessed. this bit is set by the usb sie and cleared by f/w. 2~6 unused bit, read as 0 7 mni this bit is for masking the nak interrupt when mni= 1 , the default value= 0 sies function table the misc register is actually a command + status to control the desired fifo action and to show the status of the de- sired fifo. every bit
s meaning and usage are listed as follows: bit no. function read/write register address 7 len0 r/w 01000110b 6 ready r 5 set cmd r/w 4 sel_pipe1 r/w 3 sel_pipe0 r/w 2 clear r/w 1 tx r/w 0 request r/w misc (46h) registers table
ht82j97e/ht82j97a rev. 1.60 18 december 23, 2008 function name read/write description request r/w after setting the other desired status, fifo can be requested by setting this bit high active. after work has been done, this bit must be set low. tx r/w represents the direction and transition end of the mcu accesses. when being set as logic 1, the mcu wants to write data to fifo. after work has been done, this bit must be set to logic 0 before terminating the request to represent a transition end. for reading action, this bit must be set to logic 0 to indicate that the mcu wants to read and must be set to logic 1 after work is done. clear r/w represents mcu clear requested fifo, even if fifo is not ready. sel_pipe1 sel_pipe0 r/w determines which fifo is desired, 00 for fifo 0, 01 for fifo 1 set cmd r/w shows that the data in fifo is setup as command. this bit will be cleared by firmware. so, even if the mcu is busy, nothing is missed by the setup command from the host. ready r indicates that the desired fifo is ready to work. len0 r/w indicates that the host sent a 0-sized packet to the mcu. this bit must be cleared by a read action to the corresponding fifo. also, this bit will be cleared by the usb sie after the next valid setup token is received. misc function table the ht82j97e/ht82j97a has two 8 8 bidirectional fifo for the two endpoints (control and interrupt). user can easily read/write the fifo data by accessing the corresponding fifo pointer register (fifo0, fifo1). the following are two examples for reading and writing the fifo data: ht82j97e/ht82j97a fifo is read by packet. to read from fifo, the following should be followed: select one set of fifo, set in the read mode (misc tx bit = 0), and set the req bit to 1 . check the ready bit until the status = 1 read through the fifo pointer register, and record the data number that has been read. repeat steps 2 and 3 until the ready bit becomes 0 which indicates the end of the fifo data reading. set misc tx bit = 1 clear the req bit to 0. complete reading. user reads the data through the fifo pointer register, user has to record the number of bytes to be read. the ht82j97e/ht82j97a allows a maximum of 8 bytes of data in each packet. the ht82j97e/ht82j97a fifo is written by packet. to write to fifo, the following should be followed: select a set of fifo, set in the write mode (misc tx bit = 1), and set the req bit to 1 check the ready bit until the status = 1 write through the fifo pointer register and take down the data number that has been written repeat steps 2 and 3 until writing is complete or the ready bit becomes 0 which indicates that the fifo no longer allows any data writing. set misc tx bit = 0 clear the req bit to 0. complete writing. user writes the data through the fifo pointer register, user has to record the number of bytes that have been written. the ht82j97e/ht82j97a allows a maximum of 8 bytes of data in each packet.
ht82j97e/ht82j97a rev. 1.60 19 december 23, 2008 there are some timing constrains and usages illustrated here. by setting the misc register, the mcu can perform read - ing, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writ - ing and clearing. actions misc setting flow and status read fifo0 sequence 00h 01h delay of 2 s, check 41h read* from fifo0 register and check if not ready (01h) 03h 02h write fifo1 sequence 0ah 0bh delay of 2 s, check 4bh write* to fifo1 register and check if not ready (0bh) 09h 08h check whether fifo0 can be read or not 00h 01h delay of 2 s, check 41h (if ready) or 01h (if not ready) 00h check whether fifo1 can be written to or not 0ah 0bh delay of 2 s, check 4bh (if ready) or 0bh (if not ready) 0ah write 0-sized packet sequence to fifo 0 02h 03h delay of 2 s, check 43h 01h 00h note: *: there are 2 s gap existing between 2 reading actions or between 2 writing actions register name r/w register address bit7~bit0 fifo 0 r/w 01001000b data7~data0 fifo 1 r/w 01001001b data7~data0 fifo register address table usb active pipe timing the usb active pipe accessed by the host cannot be used by the mcu simultaneously. when the host finishes its work, the signal, a usb_int will be produced to tell the mcu that the pipe can be used and the acted pipe no. will be shown in the signal, act_pipe as well. the timing is illustrated in the figure below. usb active pipe timing - b b # ! ( " ( suspend wake-up and remote wake-up if there is no signal on the usb bus for over 3ms, the ht82j97e/ht82j97a will go into a suspend mode. the suspend line (bit 0 of the usc) will be set to 1 and a usb interrupt is triggered to indicate that the ht82j97e/ht82j97a should jump to the suspend state to meet the 500 a usb suspend current spec. in order to meet the 500 a suspend current, the pro - grammer should disable the usb clock by clearing the usbcken (bit3 of the scc) to 0 . the suspend cur - rent is 400 a. the user can also further decrease the suspend current to 250 a by setting the susp2 (bit4 of the scc). but if the susp2 is set, the user has to make sure not to en - able the lvr opt option, otherwise the ht82j97e/ht82j97a will be reset. when the resume signal is sent out by the host, the ht82j97e/ht82j97a will wake-up the mcu by usb in - terrupt and the resume line (bit 3 of the usc) is set. in order to make the ht82j97e/ht82j97a function prop - erly, the programmer must set the usbcken (bit 3 of the scc) to 1 and clear the susp2 (bit4 of the scc). since the resume signal will be cleared before the idle signal is sent out by the host and the suspend line (bit 0 of the usc) is going to 0 . so when the mcu is detect - ing the suspend line (bit0 of the usc), the resume line should be remembered and taken into consideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt is triggered. the follow - ing is the timing diagram: - ( ! ( , - b
ht82j97e/ht82j97a rev. 1.60 20 december 23, 2008 the device with remote wake-up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of usc). once the usb host receive the wake-up signal from the ht82j97e/ht82j97a, it will send a resume signal to the device. the timing is as fol - lows: to configure the ht82j97e/ht82j97a as ps2 device the ht82j97e/ht82j97a can be defined as a usb in - terface or a ps2 interface by configuring the sps2 (bit 4 of the usr) and susb (bit 5 of the usr). if sps2=1, and susb=0, the ht82j97e/ht82j97a is defined as ps2 interface, pin usbd- is now defined as ps2 data pin and usbd+ is now defined as ps2 clk pin. the user can easily read or write to the ps2 data or ps2 clk pin by accessing the corresponding bit ps2dai (bit 4 of the usc), ps2cki (bit 5 of the usc), ps2dao (bit 6 of the usc) and s2cko (bit 7 of the usc) respectively. the user should make sure that in order to read the data properly, the corresponding output bit must be set to 1 . for example, if user wants to read the ps2 data by reading ps2dai, the ps2dao should be set to 1 . oth- erwise it always read a 0 . if sps2=0, and susb=1, the ht82j97e/ht82j97a is defined as a usb interface. both the usbd- and usbd+ are driven by the usb sie of the ht82j97e/ht82j97a. user only writes or reads the usb data through the corresponding fifo. both sps2 and susb default is 0 . to configure the adc block the ht82j97e/ht82j97a has built-in an 8-bit a/d con - verter with 6 channels (pb0~pb5). in order to make the a/d converter more flexible, there are two modes: exter - nal reference voltage and internal reference voltage. it can be easily configured by setting the adref (bit 6 of the usr). for external reference voltage, the refer - ence voltage of the a/d converter comes from an exter - nal pb6/vrl and pb7/vrh pins. otherwise, the reference voltage is coming from the vdd and vss of the mcu. pb0~pb5 is the 6-channel input of the a/d converter, it is easy to define which channel is converting by config - uring acs2~acs0 (bit 2~0 of the adsc). also there are four converter clock sources to be selected by setting adcs1 (bit 4 of the adsc), adcs0 ( bit 3 of the adsc). once the adon (bit 6 of the adsc) is set, it sends the start pulse through start (bit 5 of adsc). the a/d converter will be in operation. there are eocb (bit 7 of the adsc) to indicate whether the a/d converter is busy or not. the eocb is cleared when the conversion is completed. user can read the converter data by reading the register adr. in order to meet 500 a suspend cur- rent spec., user should disable the a/d by clearing adon before jumping to suspend mode. - ( ! ( , - b
+
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4 ( ( - ( # the following is an a/d converter timing diagram: , (
" ) ( 3 ! ( ! ) ( 3 ! ( ! ) ( 3 ! ) ( 3 ! ( ) ( 3 ! ( : ! $ " c b " c ) ( 3 ! ( : ! $ " ( ( ( ( ) ( 3 ! ) ( 3 ! ( ( ( ( ( 1 -
ht82j97e/ht82j97a rev. 1.60 21 december 23, 2008 to configure pwm block the ht82j97e/ht82j97a has two pwm outputs (pwm1 and pwm2), which are shared with pc2, pc3 and can be easily enabled or disabled by the pwm1_en or pwm2_en bit of port_pc (16h) respectively. also there is a one 8-bit pwmbr (pwm base period register, 18h) which defines both pwm output wave - form cycle period. pwm cycle period = 256 1/f sys (pwmbr+1), or 256 4/f sys (pwmbr+1) where 1/f sys or 4/f sys is defined by pwm_s bit of the port_pc (16h) for example if pwmbr = 17, 4/f sys (t1) is selected and f sys = 6mhz. so both output waveform cycle period is 256 4/6 (17+1) = about 3072 s (0.325khz) now user can easily define the corresponding pwm duty by configuring the pwm1dr (for pwm1) or pwm2dr (for pwm2) duty registers pwm1 duty (high pulse) = (pwm1dr+1)/256 100% pwm1 high pulse period = pwm1 duty pwm cycle pe - riod pwm1 low pulse period = pwm cycle period-high pulse period pwm2 duty (high pulse) = (pwm2dr+1)/256 100% pwm2 high pulse period = pwm2 duty pwm cycle pe - riod pwm2 low pulse period = pwm cycle period-high pulse period for example pwmbr=17, pwm1dr=63, 4/f sys (t1) is selected and f sys =6mhz pwm cycle period = 256 4/6 (17+1) = about 3072 s (0.325khz) pwm1 duty = (63+1)/256 = 25% pwm1 high pulse period = 25% 3072 s = 768 s pwm1 low pulse period = 3072 s -768 s = 2304 s +
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( , ( " i/o port special registers definition port-a (12h) pa register bits labels read/write option functions pa (12h) 0 pa0 r/w i/o (r/w) has pull-low and pull-high rom code option. has falling edge wake-up rom code option. 1 pa1 r/w i/o (r/w) has pull-low and pull-high option. has falling edge wake-up option. 2 pa2 r/w i/o (r/w) has pull-low and pull-high option. has falling edge and rising edge wake-up option. 3 pa3 r/w i/o (r/w) has pull-low and pull-high option. has falling edge and rising edge wake-up option. 4 pa4 r/w i/o (r/w) has pull-high option. has falling edge wake-up option. 5 pa5 r/w i/o (r/w) has pull-high option. has falling edge wake-up option. 6 pa6 r/w i/o (r/w) has pull-high option. has falling edge wake-up option. 7 pa7 r/w i/o (r/w) has pull-high option. has falling edge wake-up option, pin-shared with timer in - put pin. port-a control (13h) pac this port configure the input or output mode of port-a
ht82j97e/ht82j97a rev. 1.60 22 december 23, 2008 port-b control (14h) pb register bits labels read/write option functions pb (14h) 0 pb0 r/w i/o (r/w), has pull-high option, adc input. 1 pb1 r/w i/o (r/w), has pull-high option, adc input. 2 pb2 r/w i/o (r/w), has pull-low and pull-high option, adc input. 3 pb3 r/w i/o (r/w), has pull-low and pull-high option, adc input. 4 pb4 r/w i/o (r/w), has pull-high option, can wake-up, adc input. 5 pb5 r/w i/o (r/w), has pull-high option, adc input. 6 pb6 r/w i/o (r/w), has pull-high option, adc input, vrl input for adc external mode. 7 pb7 r/w i/o (r/w), has pull-high option, adc input, vrh input for adc external mode, has wake-up capability. port-b control (15h) pbc this port configures the input or output mode of port-b for i/o mode port-c control (16h) pc register bits labels read/write option functions pc (16h) 0 pc0 r/w i/o (r/w), has pull-high option 1 pc1 r/w i/o (r/w), has pull-high option 2 pc2 r/w i/o (r/w), has pull-high option, can be used as pwm1 output 3 pc3 r/w i/o (r/w), has pull-high option, can be used as pwm2 output 4 pc4 reserved bit 5 pc5 r/w pwm_s pwm base period register frequency source 0= t1 (default) 1= f sys 6 pc6 r/w pwm1_en 1: internal register bit, enable pwm1 output 0: disable (default) 7 pc7 r/w pwm2_en 1: internal register bit, enable pwm2 output 0: disable (default) port-c control (17h) pcc this port is used to control whether the port-c pin is input or output pin except pc4~pc7
ht82j97e/ht82j97a rev. 1.60 23 december 23, 2008 usb/ps2 status and control register usc (address 0x1a) register bits labels read/write option functions usc (0x1a) 0 pe0 r suspend usb suspend mode status bit. when 1, indicates that the usb system entry is in suspend mode. 1 pe1 w rmot_wk usb remote wake-up signal. default value is 0. 2 pe2 r/w urst_flag usb bus reset event flag. default value is 0. 3 pe3 r resume_o when resume_out event, resume_o is set to 1. default value is 0. 4 pe4 r ps2_dai usbd-/data input 5 pe5 r ps2_cki usbd+/clk input 6 pe6 w ps2_dao output for driving usbd-/data pin, when working un - der 3d ps2 mouse function. default value is 1. 7 pe7 w ps2_cko output for driving usbd-/data pin, when working un - der 3d ps2 mouse function. default value is 1. endpoint interrupt status register usr (address 0x1b) the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (ps2 or usb) and a/d converter operation modes. the endpoint request flags (ep0if, ep1if) are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and a usb interrupt will occur (if a usb interrupt is enabled and the stack is not full). when the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 . register bits labels read/write option functions usr (0x1b) 0 pec0 r/w ep0if when set to 1 , indicates an endpoint 0 interrupt event. must wait for the mcu to process the interrupt event and clear this bit by firmware. this bit must be 0 , then the next interrupt event will be processed. default value is 0 . 1 pec1 r/w ep1if when set to 1 , indicates an endpoint 1 interrupt event. must wait for the mcu to process the interrupt event, then clear this bit by firmware. this bit must be 0 , then the next interrupt event will be processed. default value is 0 . 2 pec2 r/w reserved bit, set to 0 3 pec3 r/w reserved bit, set to 0 4 pec4 r/w selps2 when set to 1 , indicates that the chip is working under ps2 mode. default value is 0 . 5 pec5 r/w selusb when set to 1 , indicates that the chip is working under usb mode. default value is 0. 6 pec6 r/w vrsel when set to 0 , indicates the reference voltage of the 8-bit adc from the external input pin. when set to 1 , indicates that the reference voltage is from the internal power line. default value is 1 . 7 pec7 r/w usb _flag this flag is used to show that the mcu is in usb mode (bit=1). this bit is r/w by fw and will be cleared to zero after power-on reset. the default is 0 .
ht82j97e/ht82j97a rev. 1.60 24 december 23, 2008 clock control register scc (address 0x1c) there is a system clock control register implemented to select the clock used in the mcu. this register consists of usb clock control bit (usbcken), second suspend mode control bit (suspend2) and system clock selection (sclksel). register bits labels read/write option functions scc (0x1c) 2~0 pf2~pf0 r/w reserved 3 pf3 r/w usbcken usb clock control bit. when set to 1 , indicates a usbck on, else usbck off. default value is 0 . 4 pf4 r/w suspend2 when set to 1 , enables a 7.5k resistor connected to d-pin to 5v vdd. default value is 0 . 5 pf5 r/w reserved 6 pf6 r/w sclksel system clock 6mhz or 12mhz option, when working on external oscillator mode. default value is 0 . 0: operating at external 12mhz mode 1: operating at external 6mhz mode default value is 0 . 7 pf7 r/w ps2 _flag this flag is used to show that the mcu is in ps2 mode (bit=1). this bit is r/w by fw and will be cleared to zero after power-on reset. the default is 0 . adc status and control register adc (address 0x1d) the a/d converter implemented in the mcu is a 6-channel 8-bit a/d converter. the reference voltage (high reference voltage and low reference voltage) can be selected as coming from external pins (pb6/vrl and pb7/vrh) or internal power supplies of the mcu (vdd and vss). the vrl and vrh are used to set the minimal and maximal boundaries of the full-scale range of the a/d converter. if an analog input, vrl or vrh is not used for a/d conversion, it can also be used as a general purpose i/o line. the adsc (a/d converter status and control register) register is used to set the configurations and a/d clock sources of the a/d converter and controls the operation of the a/d converter. register bits labels read/write option functions adc (0x1d) 2~0 pfc2~pfc0 r/w sel_ch these four bits selects one of the eight adc channels for conversion. channels 0 to 5 correspond to inputs ad0~ad5 on port pins pb0-pb5 respectively. chan- nels 6 and 7 are the adc reference inputs vrh and vrl, on port pins pb6 and pb7 respectively. 000: ad0 (pb0); 001: ad1 (pb1) 010: ad2 (pb2); 011: ad3 (pb3) 100: ad4 (pb4); 101: ad5 (pb5) 110: ad6 or vrl (pb6); 111: ad7 or vrh (pb7) default value is 000
b. 4~3 pfc4~pfc3 r/w sel_clk selecting adc operating clock. 00: 6mhz (default clock) 01: 3mhz 10: 1.5mhz 11: 0.75mhz 5 pfc5 r/w start start of adc conversion. high active. default value is 0 6 pfc6 r/w adon enable pin. adon=1, enable adc block. default value is 0 . 7 pfc7 r/w eocb end of conversion. this read-only status bit is cleared when a conversion is completed, indicating that the adc data register contains a valid result.
ht82j97e/ht82j97a rev. 1.60 25 december 23, 2008 adc high-byte data register adcr (address 0x1e) register bits labels read/write option functions adcr (0x1e) 7~0 pg7~pg0 r adcdr the adcdr stores the result of a valid adc conversion bit7~bit0. table high byte pointer for current table read tbhp (address 0x1f) register bits labels read/write option functions tbhp (0x1f) 2~0 pgc2~pg0 r store current table read bit10~bit8 data pwm base period register pwmbr (address 0x18) this register is used to define the base period of the pwm cycle period. the period is defined according to the following equation: base period = (4/f sys ) (pwmbr+1) or (1/f sys ) (pwmbr+1) where 4/f sys or 1/f sys is defined by pwm_s bit of port_pc where pwmbr = 1~255, pwmbr=0 is not available pwm cycle period = 256 base period base period equals to 1/256 duty cycle. register bits labels read/write option functions pwmbr (0x18) 7~0 pd7~pd0 r used to define the base period of the pwm range =2~256 base period where pwmbr=1~255, pwmbr=0 is not available pwm duty register pwm1dr (address 0xch) and pwm2dr (address 0xdh) this register is used to define the duty of the pwm1 output (pc2) or pwm2 output (pc3) respectively. both pwm cycle frequency is defined according to the following equation: register bits read/write option functions pwm1dr (0xch) pwm2dr (0xdh) 7~0 r/w used to define the pwm duty pwm1 duty = (pwm1dr+1)/pwm cycle 100% period where pwm1dr= 0~255 if the pwm function is enabled by setting the corresponding bit (pwm1_en or pwm2_en of port c), the pwm output (pc2 or pc3) pins always output the pwm signal whether the corresponding control register bit (pcc2 or pcc3 ) is de - fined as in input or output mode. otp options no. option 1 wdt clock source: rc (system/4) (default: t1) 2 wdt clock source: enable/disable for normal mode (default: disable) 3 pa0~pa7 ,pb4, pb7 wake-up by bit (pa2, pa3 both wake-up by falling or rising edge) (default: non wake-up) 4 pa0~pa7 pull-high by bit (default: pull-high) 5 pc0~3,pb pull-high by nibble (default: pull-high) 6 2.7 v (error 0.3v) lvr enable/disable (default: enable) 7 pa0~pa3, pb2, pb3 pull-low by bit (default: non pull-low 30k ) 8 clr wdt , 1 or 2 instructions 9 tbhp enable/disable (default: disable) 10 pa output mode (cmos/nmos/pmos) by bit (default: cmos) the lvr voltage is define as 2.7v 0.3v and default is enable.
application circuits crystal or ceramic resonator for multiple i/o applications note: the resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. x1 can use 6mhz or 12mhz, x1 as close osc1 & osc2 as possible components with * are used for emc issue. components with ** are used for resonator only. components with *** are used for 12mhz application. crystal or ceramic resonator for multiple i/o applications note: x1 can use 6mhz or 12mhz, x1 as close osc1 & osc2 as possible components with * are used for resonator only. ht82j97e/ht82j97a rev. 1.60 26 december 23, 2008 - 5 ) # - 6 ) 7 7 4 / > : - 6 - 5 7 7 7 7 . 1 - . - 1 . 7 4 : * 1 : f * 1 : f f f / 4 : f f / f * 1 : f * 1 : f 4 : > 7 7 f 4 : : : 4 : > f f f f f f
f f f - 5 ) # - 6 ) 7 7 4 / > : - 6 - 5 . 1 - . - 1 . 1 4 : 4 : > 4 : f f . 1
ht82j97e/ht82j97a rev. 1.60 27 december 23, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht82j97e/ht82j97a rev. 1.60 28 december 23, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht82j97e/ht82j97a rev. 1.60 29 december 23, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht82j97e/ht82j97a rev. 1.60 30 december 23, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht82j97e/ht82j97a rev. 1.60 31 december 23, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht82j97e/ht82j97a rev. 1.60 32 december 23, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht82j97e/ht82j97a rev. 1.60 33 december 23, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht82j97e/ht82j97a rev. 1.60 34 december 23, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht82j97e/ht82j97a rev. 1.60 35 december 23, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht82j97e/ht82j97a rev. 1.60 36 december 23, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht82j97e/ht82j97a rev. 1.60 37 december 23, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht82j97e/ht82j97a rev. 1.60 38 december 23, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht82j97e/ht82j97a rev. 1.60 39 december 23, 2008
package information 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c
496 512 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht82j97e/ht82j97a rev. 1.60 40 december 23, 2008 - : g & 2
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in mil min. nom. max. a 393 419 b 256 300 c12 20 c
697 713 d 104 e 50 f4 12 g16 50 h8 13 0 8 ht82j97e/ht82j97a rev. 1.60 41 december 23, 2008 9 / * - : g & 2
product tape and reel specifications reel dimensions sop 20w symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 ht82j97e/ht82j97a rev. 1.60 42 december 23, 2008 -
carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.8 0.1 b0 cavity width 13.3 0.1 k0 cavity depth 3.2 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 21.3 0.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.10 b0 cavity width 18.34 0.10 k0 cavity depth 2.97 0.10 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 0.1 ht82j97e/ht82j97a rev. 1.60 43 december 23, 2008 + : - ( > ( ( ( " ( $ ( , ( $ , ! ( , " ( ( $ ( ! ( ! " 4 , ( 2 ,
ht82j97e/ht82j97a rev. 1.60 44 december 23, 2008 copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) g room, 3 floor, no.1 building, no.2016 yi-shan road, minhang district, shanghai, china 201103 tel: 86-21-5422-4590 fax: 86-21-5422-4705 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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